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Military QuickRAM
90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM
Military QuickRAM
DEVICE HIGHLIGHTS
Device Highlights Features
FEATURES
Total of 316 I/O pins
s
High Performance and High Density
s s
Up to 90,000 Usable PLD Gates with 316 I/Os 300 MHz 16-bit Counters, 400 MHz Datapaths, 160+ MHz FIFOs 0.35um four-layer metal non-volatile CMOS process for smallest die sizes
308 bi-directional input/output pins, PCI-compliant for 5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades 8 high-drive input/distributed network pins
s
s
Eight Low-Skew Distributed Networks
s
High Speed Embedded SRAM
s
Up to 22 dual-port RAM modules, organized in userconfigurable 1,152-bit blocks 5ns access times, each port independently accessible Fast and efficient for FIFO, RAM, and ROM functions
Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs - each driven by an input-only pin Six global clock/control networks available to the logic cell F1, clock, set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback
s
s s
Easy to Use / Fast Development Cycles
s
100% routable with 100% utilization and complete pin-out stability Variable-grain logic cells provide high performance and 100% utilization Comprehensive design tools include high quality Verilog/ VHDL synthesis
High Performance
s s s s
Input + logic cell + output total delays under 6 ns Data path speeds exceeding 400 MHz Counter speeds over 300 MHz FIFO speeds over 160+ MHz
s
s
Advanced I/O Capabilities
s s
Military Reliability
s s
Interfaces with both 3.3 volt and 5.0 volt devices PCI compliant with 3.3V and 5.0V buses for -1/-2 speed grades Full JTAG boundary scan Registered I/O cells with individually controlled clocks and output enables
Device
QL4016 11,520 RAM Bits
Mil-STD-883 and Miil Temp Ceramic Mil Temp Plastic - Guaranteed -55C to 125C
s s
Usable Gates
8,00016,000
Package
Max I/O
70 70 82 118 174 174 174 174 207 223 316
Qualification Level
M, /883 M M, /883 M, /883 M M, /883 M M, /883 M M, /883 M
Supply Voltage
3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3V 3.3V 3.3V 3.3V 3.3V
84CPGA 84PLCC 100CQFP 144CPGA QL4036 16,000208PQFP 16,128 RAM bits 25,000 208CQFP 208PQFP 208CQFP QL4090 36,000240PQFP 25,344 RAM bits 60,000 256CPGA 456PBGA M = Military Temperature (-15 to +125 degrees C) /888 = MIL STD 883
TABLE 1: Selector Table
Rev A
8-37
Military QuickRAM
PRODUCT SUMMARY
Product Summary
The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with Dual-Port SRAM modules. QuickRAM is a 90,000 usable PLD gate ESPs. QuickRAM ESPs are fabricated on a 0.35mm four-layer metal process using QuickLogic's patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. QuickRAM contains up to 1,584 logic cells and 22 dual port RAM modules. Each RAM module has 1,152 RAM bits, for a total of up to 25,344 bits. RAM Modules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2. With a maximum of 316 I/Os, and is availPinout Diagram 84-Pin PLCC
able in plastic 84-PLCC, 208-PQFP, 240-PQFP and 456-PBGA packages and in ceramic 100, 208CQFP and 84, 144, 256-CPGA. Software support for the complete QuickRAM family is available through two basic packages. The turnkey QuickWorks package provides the most complete ESP software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest, or other third-party tools for design entry, synthesis, or simulation.
PINOUT DIAGRAM 84-PIN PLCC
QuickRAM QL4016-1PL84M
TABLE 2: 84-pin PLCC
8-38 38 Rev A
Preliminary
Military QuickRAM
PINOUT DIAGRAM 100-PIN CQFP
Pinout Diagram 100-Pin CQFP
Pin #1
Pin #76
QuickRAM QL4016-1CF100M
Pin #26
Pin #51
100 CQFP Pinout Table
100 TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK / I ACLK / I VCC GCLK / I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O 100 100 100 Function Function Function TQFP TQFP TQFP 26 TDI 51 I/O 76 TCK 27 I/O 52 I/O 77 STM 28 I/O 53 I/O 78 I/O 29 I/O 54 I/O 79 I/O 30 I/O 55 I/O 80 I/O 31 I/O 56 I/O 81 I/O 32 I/O 57 I/O 82 I/O 33 I/O 58 I/O 83 I/O 34 I/O 59 GND 84 I/O 35 GND 60 I/O 85 GND 36 I/O 61 GCLK / I 86 I/O 37 I/O 62 ACLK / I 87 I/O 38 GND 63 VCC 88 GND 39 I/O 64 GCLK / I 89 I/O 40 I/O 65 GCLK / I 90 I/O 41 I/O 66 VCC 91 I/O 42 VCCIO 67 I/O 92 VCCIO 43 I/O 68 I/O 93 I/O 44 I/O 69 I/O 94 I/O 45 I/O 70 I/O 95 I/O 46 I/O 71 I/O 96 I/O 47 I/O 72 I/O 97 I/O 48 I/O 73 I/O 98 I/O 49 TRSTB 74 I/O 99 I/O 50 TMS 75 I/O 100 TDO
Rev A
8-39
Military QuickRAM
PINOUT DIAGRAMS
208-Pin PQFP/CQFP
Pin #1 Pin #157
QuickRAM QL4090-1PQ208M
Pin #53
Pin #105
240-Pin PQFP
Pin #157 Pin #1
QuickRAM QL4090-1PQ240M
Pin #53
Pin #105
8-40 40
Rev A
Preliminary
Military QuickRAM
PINOUT TABLE
PQFP/CQFP 240/208 Pinout Table
240 208 PQFP PQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 208 1 2 3 4 5 NC 6 7 8 9 10 11 12 13 14 NC 15 16 17 18 19 20 NC 21 22 23 24 25 26 27 28 29 30 31 32 NC 33 NC 34 35 36 NC 37 38 39 NC 40 41 42 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK / I ACLK / I VCC GCLK / I GCLK / I VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O 240 208 PQFP PQFP 51 52 53 54 55 56 57 58 59 60 NC NC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC 84 85 86 87 88 89 90 91 92 93 94 95 96 97 43 44 45 46 47 48 NC 49 50 51 52 53 54 NC NC 55 56 NC 57 58 59 60 61 62 63 64 NC 65 66 67 NC 68 69 70 NC 71 NC 72 73 74 NC 75 76 77 78 79 80 81 82 83 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O GND I/O I/O I/O I/O VCCIO 240 208 PQFP PQFP 98 99 100 101 102 103 104 105 106 107 108 109 110 NC 111 NC NC 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 84 85 86 87 88 89 90 91 92 NC 93 94 95 96 97 98 99 100 NC 101 NC 102 NC NC 103 104 105 NC 106 107 108 109 NC 110 111 112 113 114 115 116 117 NC 118 119 120 121 NC 122 123 124 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 240 208 Function PQFP PQFP 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 NC 181 182 183 184 185 186 187 188 189 190 191 192 193 125 126 127 128 NC 129 130 131 132 133 134 135 136 NC 137 NC 138 139 140 141 142 NC 143 144 145 NC 146 147 148 149 150 151 152 153 154 155 156 157 158 NC 159 160 161 162 163 164 165 166 NC 167 I/O I/O GND I/O I/O GCLK / I ACLK / I VCC GCLK / I GCLK / I VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O 240 208 PQFP PQFP 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 168 169 NC 170 171 172 173 174 175 NC 176 177 178 179 NC 180 181 182 NC 183 184 185 186 187 188 NC 189 190 191 192 193 194 NC 195 196 197 198 NC 199 200 201 202 203 204 205 206 207 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO
Rev A
8-41
Military QuickRAM
PINOUT DIAGRAM 84-PIN CPGA
Pinout Diagram 84-Pin CPGA
QuickRAM QL4016-1CG84M
84-Pin CPGA Pinout Table
84 CPGA A1
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
Function I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO I/O TDI I/O I/O GCLK / I GCLK / I GCLK / I I/O I/O I/O
84 CPGA B11
C1 C2 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 E11 F1 F2 F3
Function I/O
VCC I/O VCC ACLK / I GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O I/O I/O I/O I/O
84 CPGA F9
F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 J1 J2 J5 J6 J7 J10 J11 K1
Function I/O
I/O I/O I/O I/O VCCIO GND I/O I/O I/O I/O VCC I/O I/O TRSTB GND ACLK / I VCC STM I/O I/O
84 CPGA K2
K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
Function I/O
I/O I/O GCLK / I GCLK / I GCLK / I I/O I/O TCK I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
8-42 42
Rev A
Preliminary
Military QuickRAM
PINOUT DIAGRAMS 144 & 256-PIN CPGAS
Pinout Diagrams 144 & 256-Pin CPGAs
QuickRAM QL4036-1CG144M
144-Pin CPGA
1 2 3 4 5 6 7 8 9 10 1 121314151617181920 1
Y W V U T R P N M L K J H G F E D C B A
QuickRAM QL4090-1CG256M
256-Pin CPGA
Rev A 8-43
Military QuickRAM
PINOUT TABLE 144-PIN CPGA
Pinout Table 144-Pin CPGA
144 CPGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 C6 8-44 44
Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O TDO I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O STM I/O I/O I/O I/O I/O I/O GND I/O
144 CPGA C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D13 D14 D15 E1 E2 E3 E13 E14 E15 F1 F2 F3 F13 F14 F15 G1 G2 G3 G13 G14 G15 H1 H2 H3
Function I/O GND I/O I/O I/O TCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O GCLK / I GND I/O I/O VCC VCC GCLK / I GCLK / I I/O ACLK / I
144 CPGA H13 H14 H15 J1 J2 J3 J13 J14 J15 K1 K2 K3 K13 K14 K15 L1 L2 L3 L13 L14 L15 M1 M2 M3 M13 M14 M15 N1 N2 N3 N4 N5 N6 N7 N8 N9
Function ACLK / I I/O GCLK / I GCLK / I VCC VCC I/O I/O GND GCLK / I I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O
144 CPGA N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Function I/O GND I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O TRSTB I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O TMS
Rev A
Preliminary
Military QuickRAM
PINOUT TABLE 256-PIN CPGA
Pinout Table 256-Pin CPGA
256 CPGA
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3
Function
VCC I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O GND I/O TCK I/O I/O I/O GND I/O I/O I/O VCCIO I/O VCC I/O GND I/O I/O I/O VCC I/O GND I/O I/O I/O I/O TDO
256 CPGA
C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18
Function
I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O STM I/O I/O I/O I/O I/O I/O I/O I/O I/O
256 CPGA
E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1
Function
I/O VCC I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O VCC GND VCC ACLK / I VCC GND GCLK / I I/O I/O GCLK / I GCLK / I GCLK / I
256 CPGA
L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4
Function
GCLK / I GND I/O GCLK / I I/O VCC ACLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O GND I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O I/O VCC
256 CPGA
T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
Function
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O GND I/O GND TMS I/O
256 CPGA
V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
Function
I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND I/O VCCIO I/O I/O I/O I/O I/O TRSTB I/O TDI I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O
Rev A
8-45
Military QuickRAM
PINOUT DIAGRAM 456-PIN PBGA
Pinout Diagram 456-Pin PBGA
QuickRAM
M QL4090-1PB456C
456 Pin PBGA TOP
PIN A1 CORNER
Bottom
8-46 46
Rev A
Preliminary
Military QuickRAM
PINOUT TABLE 456-PIN PBGA
Pinout Table 456-Pin PBGA 456 Function
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 456 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 Function STM I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK I/O I/O I/O I/O GND I/O NC I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O NC I/O GND I/O 456 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 Function I/O I/O I/O I/O I/O I/O GND VCC GND NC GND I/O GND GND VCC GND GND GND NC GND NC GND VCC GND I/O I/O I/O I/O I/O I/O I/O NC VCC VCC NC I/O I/O I/O I/O I/O I/O I/O NC GND I/O I/O I/O I/O I/O I/O I/O 456 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 Function I/O NC NC I/O I/O I/O I/O I/O I/O I/O NC GND NC NC I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC I/O I/O I/O I/O ACLK / I GCLK/I I/O NC GND GND/THERM GND/THERM GND/THERM 456 M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 Function GND/THERM GND/THERM GND/THERM NC NC I/O I/O I/O GCLK/I I/O I/O GCLK/I VCC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND I/O I/O I/O I/O I/O I/O I/O I/O NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC GCLK / I GCLK / I I/O ACLK / I I/O I/O I/O NC NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM (Cont'd on next page)
Rev A
8-47
Military QuickRAM
PBGA 456 Pinout Table
(continued from previous page)
456 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Function VCC NC I/O I/O GCLK / I I/O I/O I/O I/O VCC GND/THERMAL GND/THERMAL GND/THERMAL GND/THERMAL GND/THERMAL GND/THERMAL GND I/O I/O I/O I/O I/O I/O I/O I/O GND NC I/O I/O I/O I/O I/O I/O I/O NC NC GND NC I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O 456 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 Function I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O NC NC VCC VCC NC I/O I/O I/O I/O I/O I/O I/O GND VCC NC NC NC VCC GND NC I/O GND VCC I/O NC VCC GND NC VCC GND I/O I/O I/O I/O I/O I/O NC GND I/O 456 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 Function NC I/O I/O NC I/O I/O NC I/O VCCIO NC I/O I/O NC I/O I/O I/O NC GND I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB I/O I/O I/O TDI I/O I/O I/O 456 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
8-48 48
Rev A
Preliminary
Military QuickRAM
Pin Descriptions
PIN DESCRIPTIONS
Pin TDI/RSI TRSTB/RRO TMS TCK TDO/RCO STM I/ACLK I/GCLK I I/O VCC VCCIO GND GND/THERM
Function Test Data In for JTAG / RAM init. Serial Data In Active low Reset for JTAG / RAM init. reset out Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG / RAM init. clock out Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-drive input Input/Output pin Power supply pin Input voltage tolerance pin Ground pin Ground/Thermal pin
Description
Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused. Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization. Must be grounded during normal operation. Can be configured as either or both. Can be configured as either or both. Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3V supply. Connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3V supply. Connect to ground. Available on 456-PBGA only. Connect to ground plane on PCB if heat sinking desired. Otherwise may be left unconnected.
Ordering Information
QL 4090 - 1 PQ208 M
QuickLogic device QuickRAM device part number 4016 4036 4090 Speed Grade 0 = quick 1 = fast 2 = faster Operating Range M = Military M/883 = MIL STD 883 Package Code PL84 = 84-pin PLCC CG84=84-pin CPGA CF100 = 100-pin CQFP CG144=144-pin CPGA PQ208 = 208-pin PQFP CF208 = 208-pin CQFP PQ240 = 240-pin PQFP CG256=256-pin CPGA CG456=456-pin PBGA
Rev A
8-49
Military QuickRAM
ABSOLUTE MAXIMUM RATINGS
VCC Voltage ...........................-0.5 to 4.6V VCCIO Voltage .......................-0.5 to 7.0V Input Voltage.............. -0.5 to VCCIO+0.5V Latch-up Immunity ...................200 mA DC Input Current...................... 20 mA ESD Pad Protection.................... 2000V Storage Temperature .......-65C to +150C Lead Temperature ...........................300C
OPERATING RANGE
Symbol VCC VCCIO TA TC K Parameter Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature Delay Factor -0 Speed Grade -1 Speed Grade -2 Speed Grade Min 3.0 3.0 -55 0.42 0.42 0.42 Military Max 3.6 5.5 125 2.03 1.64 1.37 Unit V V C C
DC CHARACTERISTICS
Symbol VIH VIL VOH VOL II IOZ CI IOS ICC ICCIO Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [2] Output Short Circuit Current [3] D.C. Supply Current [4] D.C. Supply Current on VCCIO Min Max Unit 0.5VCC VCCIO+0.5 V -0.5 0.3VCC V IOH = -12 mA 2.4 V 0.9VCC V IOH = -500 A IOL = 8 mA [1] 0.45 V IOL = 1.5 mA 0.1VCC V VI = VCCIO or GND -10 10 A VI = VCCIO or GND -10 10 A 10 pF VO = GND -15 -180 mA VO = VCC 40 210 mA VI, VIO = VCCIO or GND 0.50 (typ) 5 mA 0 100 A Conditions
Notes: [1] Military devices have 8 mA IOL specifications. [2] Capacitance is sample tested only. Clock pins are 12 pF maximum. [3] Only one output at a time. Duration should not exceed 30 seconds. [4] Maximum ICC is 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer engineering.
8-50 50
Rev A
Preliminary
Military QuickRAM
QL4016
QL4016
AC CHARACTERISTICS at VCC = 3.3V, TA = 25C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)
Logic Cells
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [7] Setup Time [7] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 Propagation Delays (ns) Fanout [6] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
Input-Only/Clock Cells
Symbol TIN TINI TISU TIH TlCLK TlRST TlESU TlEH Parameter
1
Propagation Delays (ns) Fanout [6]
2 3 4 8 12 24
High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time
1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0
1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0
1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0
1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0
2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0
2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0
4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
Notes: [6] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [7] These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
Rev A
8-51
Military QuickRAM
QL4016 Clock Cells
Symbol tACK tGCKP tGCKB Parameter Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1 1.2 0.7 0.8 Propagation Delays (ns) Loads per Half Column [8] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2
11 1.7 0.7 1.3
I/O Cell Input Delays
Symbol
tI/O TISU TIH TlOCLK TlORST TlESU TlEH
Parameter
1 Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time
Propagation Delays (ns) Fanout [6]
2 3 4 8 10
1.3 3.1 0.0 0.7 0.6 2.3 0.0
1.6 3.1 0.0 1.0 0.9 2.3 0.0
1.8 3.1 0.0 1.2 1.1 2.3 0.0
2.1 3.1 0.0 1.5 1.4 2.3 0.0
3.1 3.1 0.0 2.5 2.4 2.3 0.0
3.6 3.1 0.0 3.0 2.9 2.3 0.0
I/O Cell Output Delays
Symbol
TOUTLH TOUTHL TPZH TPZL TPHZ TPLZ
Parameter
30 Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [9] Output Delay Low to Tri-State [9]
Propagation Delays (ns) Output Load Capacitance (pF)
50 75 100 150
2.1 2.2 1.2 1.6 2.0 1.2
2.5 2.6 1.7 2.0
3.1 3.2 2.2 2.6
3.6 3.7 2.8 3.1
4.7 4.8 3.9 4.2
Notes: [6] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [8] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column. [9] The following loads are used for tPXZ:
tPHZ 1K 5 pF 1K tPLZ 5 pF
8-52 52
Rev A
Preliminary
Military QuickRAM
QL4036
QL4036
AC CHARACTERISTICS at VCC = 3.3V, TA = 25C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)
Logic Cells
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
Input-Only/Clock Cells
Symbol TIN TINI TISU TIH TlCLK TlRST TlESU TlEH Parameter
1
Propagation Delays (ns) Fanout [5]
2 3 4 8 12 24
High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time
1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0
1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0
1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0
1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0
2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0
2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0
4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined fromtiming analysis of your particular design.
Rev A
8-53
Military QuickRAM
QL4036 Clock Cells
Symbol tACK tGCKP tGCKB Parameter Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1 1.2 0.7 0.8 Propagation Delays (ns) Loads per Half Column [7] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2 12 1.7 0.7 1.3 15 1.8 0.7 1.4
I/O Cell Input Delays
Symbol
tI/O TISU TIH TlOCLK TlORST TlESU TlEH
Parameter
1 Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time
Propagation Delays (ns) Fanout [5]
2 3 4 8 10
1.3 3.1 0.0 0.7 0.6 2.3 0.0
1.6 3.1 0.0 1.0 0.9 2.3 0.0
1.8 3.1 0.0 1.2 1.1 2.3 0.0
2.1 3.1 0.0 1.5 1.4 2.3 0.0
3.1 3.1 0.0 2.5 2.4 2.3 0.0
3.6 3.1 0.0 3.0 2.9 2.3 0.0
I/O Cell Output Delays
Symbol
TOUTLH TOUTHL TPZH TPZL TPHZ TPLZ
Parameter
30 Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8]
Propagation Delays (ns) Output Load Capacitance (pF)
50 75 100 150
2.1 2.2 1.2 1.6 2.0 1.2
2.5 2.6 1.7 2.0
3.1 3.2 2.2 2.6
3.6 3.7 2.8 3.1
4.7 4.8 3.9 4.2
Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [7] The array distributed networks consist of 56 half columns and the global distributed networks consist of 60 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 12 loads per half column. The global clock has up to 15 loads per half column. [8] The following loads are used for tPXZ:
tPHZ 1K 5 pF 1K tPLZ 5 pF
8-54 54
Rev A
Preliminary
Military QuickRAM
QL4090
QL4090
AC CHARACTERISTICS at VCC = 3.3V, TA = 25C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)
Logic Cells
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8
8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
Input-Only/Clock Cells
Symbol TIN TINI TISU TIH TlCLK TlRST TlESU TlEH Parameter
1
Propagation Delays (ns) Fanout [5]
2 3 4 8 12 24
High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time
1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0
1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0
1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0
1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0
2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0
2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0
4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
Rev A
8-55
Military QuickRAM
QL4090 Clock Cells
Symbol
TACK TGCKP TGCKB
Parameter
Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1 1.2 0.7 0.8 2 1.2 0.7 0.8 3 1.3 0.7 0.9
Propagation Delays (ns) Loads per Half Column [7]
4 1.3 0.7 0.9 8 1.5 0.7 1.1 10 1.6 0.7 1.2 12 1.7 0.7 1.3 14 1.8 0.7 1.4 16 1.9 0.7 1.5 18 2 0.7 1.6 20 2.1 0.7 1.7
I/O Cell Input Delays
Symbol
tI/O TISU TIH TlOCLK TlORST TlESU TlEH
Parameter
1 Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time
Propagation Delays (ns) Fanout [5]
2 3 4 8 10
1.3 3.1 0.0 0.7 0.6 2.3 0.0
1.6 3.1 0.0 1.0 0.9 2.3 0.0
1.8 3.1 0.0 1.2 1.1 2.3 0.0
2.1 3.1 0.0 1.5 1.4 2.3 0.0
3.1 3.1 0.0 2.5 2.4 2.3 0.0
3.6 3.1 0.0 3.0 2.9 2.3 0.0
I/O Cell Output Delays
Symbol
TOUTLH TOUTHL TPZH TPZL TPHZ TPLZ
Parameter
30 Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8]
Propagation Delays (ns) Output Load Capacitance (pF)
50 75 100 150
2.1 2.2 1.2 1.6 2.0 1.2
2.5 2.6 1.7 2.0
3.1 3.2 2.2 2.6
3.6 3.7 2.8 3.1
4.7 4.8 3.9 4.2
Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [7] The array distributed networks consist of 88 half columns and the global distributed networks consist of 92 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 18 loads per half column. The global clock has up to 20 loads per half column. [8] The following loads are used for tPXZ:
tPHZ 1K 5 pF 1K tPLZ 5 pF
8-56 56
Rev A
Preliminary
Military QuickRAM
RAM Cell Synchronous Write Timing
Symbol TSWA THWA TSWD THWD TSWE THWE TWCRD Parameter WA Setup Time to WCLK WA Hold Time to WCLK WD Setup Time to WCLK WD Hold Time to WCLK WE Setup Time to WCLK WE Hold Time to WCLK WCLK to RD (WA=RA) [5] 1 1.0 0.0 1.0 0.0 1.0 0.0 5.0 Propagation Delays (ns) Fanout 2 3 4 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 5.3 5.6 5.9
8 1.0 0.0 1.0 0.0 1.0 0.0 7.1
RAM Cell Synchronous Read Timing
Symbol TSRA THRA TSRE THRE TRCRD Parameter RA Setup Time to RCLK RA Hold Time to RCLK RE Setup Time to RCLK RE Hold Time to RCLK RCLK to RD [5] 1 1.0 0.0 1.0 0.0 4.0 Propagation Delays (ns) Fanout 2 3 4 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 4.3 4.6 4.9
8 1.0 0.0 1.0 0.0 6.1
RAM Cell Asynchronous Read Timing
Symbol RPDRD Parameter RA to RD [5] 1 3.0 Propagation Delays (ns) Fanout 2 3 4 3.3 3.6 3.9
8 5.1
Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
Rev A
8-57
Military QuickRAM
8-58 58
Rev A
Preliminary

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